Due to advancing semiconductor processing technology, integrated circuits (ICs) have greatly increased in functionality and complexity. For example, ICs such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), microprocessors and programmable logic devices (PLDs), can incorporate ever-increasing numbers of functional logic blocks and more flexible interconnect structures to provide greater functionality and flexibility.
FIG. 1 is a simplified schematic diagram of a conventional FPGA 110. FPGA 110 includes user logic circuits such as input/output blocks (IOBs), configurable logic blocks (CLBs), and programmable interconnect 130, which contains programmable switch matrices (PSMs). Furthermore, FPGA 110 contains bonding pads (PADs) to connect the various user logic circuits to pins (not shown) of FPGA 110. In some FPGAs, the PADs are incorporated as part of the IOBs. Each IOB and CLB can be configured through configuration port 120 to perform a variety of functions. Configuration port 120 is typically coupled to external pins of FPGA 110 through various bonding pads. Programmable interconnect 130 can be configured to provide electrical connections between the various CLBs and IOBs by configuring the PSMs and other programmable interconnection points (PIPS, not shown) through configuration port 120. Typically, the IOBs can be configured to drive output signals or to receive input signals from the corresponding PADs of FPGA 110.
FPGA 110 also includes dedicated internal logic. Dedicated internal logic performs specific functions and can only be minimally configured by a user. For example, configuration port 120 is one example of dedicated internal logic. Other examples may include dedicated clock nets (not shown), power distribution grids (not shown), and boundary scan logic (i.e. IEEE Boundary Scan Standard 1149.1, not shown).
FPGA 110 is illustrated with 16 CLBs, 16 IOBS, 9 PSMs, and 16 PADs for clarity only. Actual FPGAs may contain thousands of CLBS, thousands of PSMs, hundreds of IOBS, and hundreds of PADs. Furthermore, FPGA 110 is not drawn to scale. For example, a typical PAD occupies far more area than a CLB, PSM, or IOB. The ratio of the number of CLBs, IOBs, PSMs, and PADs can also vary.
FPGA 110 also includes dedicated configuration logic circuits to program the user logic circuits. Specifically, each CLB, IOB, PSM, and PIP contains a configuration memory (not shown) which must be configured before each CLB, IOB, PSM, or PIP can perform a specified function. Typically the configuration memories within an FPGA use static random access memory (SRAM) cells. The configuration memories of FPGA 110 are connected by a configuration structure (not shown) to configuration port 120 through a configuration access port (CAP) 125. A configuration port (a set of pins used during the configuration process) provides an interface for external configuration devices to program the FPGA. The configuration memories are typically arranged in rows and columns. The columns are loaded from a frame register which is in turn sequentially loaded from one or more sequential bitstreams. (The frame register is part of the configuration structure referenced above.) In FPGA 110, configuration access port 125 is essentially a bus access point that provides access from configuration port 120 to the configuration structure of FPGA 110.
FIG. 2 illustrates a conventional method used to configure FPGA 110. Specifically, FPGA 110 is coupled to a configuration device 230 such as a serial programmable read only memory (SPROM), an electrically programmable read only memory (EPROM), or a microprocessor. Configuration port 120 receives configuration data, usually in the form of a configuration bitstream, from configuration device 230. Typically, configuration port 120 contains a set of mode pins, a clock pin and a configuration data input pin. Configuration data from configuration device 230 is transferred serially to FPGA 110 through the configuration data input pin. In some embodiments of FPGA 110, configuration port 120 comprises a set of configuration data input pins to increase the data transfer rate between configuration device 230 and FPGA 110 by transferring data in parallel. However, due to the limited number of dedicated function pins available on an FPGA, configuration port 120 usually has no more than eight configuration data input pins. Further, some FPGAs allow configuration through a boundary scan chain. Specific examples for configuring various FPGAs can be found on pages 4-46 to 4-59 of "The Programmable Logic Data Book", published in January, 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. Additional methods to program FPGA's are described by Lawman in commonly assigned, co-pending U.S. patent application Ser. No. 09/000,519, entitled "DECODER STRUCTURE AND METHOD FOR FPGA CONFIGURATION" by Gary R. Lawman, which is referenced above.
As explained above, actual FPGAs can have thousands of CLBS, IOBs, PSMs, and PIPS. Furthermore, as semiconductor processing techniques improves, FPGAs of greater and greater complexity can be created. However, processing techniques for bonding pads and pins for integrated circuits have not evolved as rapidly as semiconductor processing techniques. Consequently, complex integrated circuits such as ASICs, microprocessors, and FPGAs are increasingly pad limited rather than circuit limited. Thus, manufacturers of integrated circuits can provide more functionality in an integrated circuit than a customer may need.
However, many customers are unwilling to pay for the unneeded functionality. Therefore, manufacturers of integrated circuits must provide multiple product lines having different functionality at different price points. For example, manufacturers of FPGAs may provide FPGA product lines having differing numbers of CLBs and PSMs. However, each product line entails development and manufacturing costs for the manufacturer of the integrated circuit. Furthermore, the manufacturer may misjudge market demands for different product lines and cause shortages of one product line and excess inventory in another product line. Hence, there is a need for a method or structure to satisfy differing needs of customers for integrated circuit functionality, without the cost and risk of creating multiple ICs to support multiple product lines.